In an ongoing Google AI blog entry, lead Jeff Dean, researchers at Google Research and the Google chip execution and framework group portrayed an AI innovation that can structure PC contributes under six hours.
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According to the company, the new technology advances the state of the art in that it implies the placement of on-chip transistors can be largely automated. If made publicly available, the Google researchers’ technique could enable cash-strapped startups to develop their chips for AI and other specialized purposes.
According to the researchers, “Unlike existing methods that optimise the placement for each new chip from scratch, our work leverages knowledge gained from placing prior chips to become better over time.”
Additionally, “our method enables direct optimisation of the target metrics, such as wirelength, density, and congestion, without having to define … approximations of those functions as is done in other approaches. Not only does our formulation make it easy to incorporate new cost functions as they become available, but it also allows us to weigh their relative importance according to the needs of a given chip block (e.g., timing-critical or power-constrained),” concluded the researchers.